1. Field of the Invention
The present invention is related to integrated circuits (IC) having external terminals. More particularly, the present invention is directed to IC packages that hold an integrated circuit (i.e., electronic circuit chip) therein that is electrically connected to terminals of the IC package that extend outside of the package, and are thus termed external terminals, which are formed in plural steps. The plural steps of external terminals reduces the required area (i.e., footprint) required to support the IC package on a circuit board.
2. Discussion of the Related Art
One type of IC package is described in Japanese Unexamined Patent Publication (KOKAI) No. 6-61363. This IC package attempts to prevent the external terminals of the IC package from being transformed in shape during ordinary use, by locating the wide portions of the external terminals in a hounds-tooth configuration so as to keep limited clearance between the respective terminals.
Electric circuit chips may be reduced in area by way of improvements in semiconductor manufacturing processes. However, simply by reducing the size of the chip does not solve a problem regarding how to package the chip in a configuration that provides terminals that may be easily electrically and physically connected to circuit boards. A limitation with the package itself regards the lead pitch (i.e., the relative spacing between external terminals) in order to meet manufacturing tolerances, physical restrictions on board use, and electrical considerations regarding isolation between the terminals. Thus, even if further reductions in chip size are possible, when the chips are placed within the package the overall package size is not necessarily reduced because the pitch of the external pins for the package limits the overall footprint of the device.
Some packages such as Quad Flat Package (QFP) have a feature that allows pin pitch to be 0.4 mm, as a limit generally. Accordingly, in these configurations, even though the chip size is reduced, the overall package size once again is limited by the pin pitch, commonly restricted to 0.4 mm. In products that require a large number of external pins, there is the distinct possibility that the size of the package will be 10 times as large as the chip itself (when comparing the respective footprints of the chip and the package).
FIG. 2 is an example of a conventional package and chip, which is viewed from a top view. A pitch of the external terminals in this case is required to be more than 0.4 mm and as a general rule for manufacturing and reliability purposes cannot be less than 0.4 mm. Accordingly, the size of this package 12, as shown in FIG. 2, is larger than the internal chip 10, and the distance between the package 12 and the chip 10 results in a significant amount of useless space around the chip that takes up perhaps valuable real estate on a circuit board. Conventional approaches have not adequately addressed this problem, as determined by the present inventor.
Moreover, using conventional techniques, it has not been possible for the overall IC package to be reduced in size due to a requirement of maintaining a minimum lead pitch. However, with more complex chips that require additional external pins, the overall package size of products has been increasing, yet the amount of real estate allocated for more modern IC components is being reduced as modern electronic are generally shrinking in size.